1. Field of the Invention
The present invention relates generally to integrated circuits, and in particular, to a novel method of single data line sensing of thinly capacitively-coupled thyristor (“TCCT”)-based memory cells.
2. Description of Related Art
U.S. Pat. No. 6,229,161 issued to Nemati et al., incorporated herein by reference in its entirety, discloses capacitively coupled NDR devices for use as SRAM memory cells. The cells disclosed by Nemati et al. are hereinafter referred to as thinly capacitively coupled thyristor (“TCCT”) based memory cells. FIG. 1 shows a pair of representative TCCT based memory cells 10 as disclosed by Nemati et al., and FIG. 2 shows a cross-section through one TCCT based memory cell 10 along the line 2-2. FIG. 3 shows a schematic circuit diagram corresponding to the embodiment illustrated in FIGS. 1 and 2. The TCCT based memory cell 10 includes an NDR device 12 and a pass transistor 14. A charge-plate or gate-like device 16 is disposed adjacent to, and in the case of the illustrated embodiment, surrounding, the NDR device 12. A P+ region 18 of the NDR device 12 is connected to a metallization layer 20 so that a first voltage V1, such as Vddarry, can be applied to the NDR device 12 through the P+ region 18. An N+ region of the NDR device 12 forms a storage node 22 that is connected to a source of the pass transistor 14. Where the pass transistor 14 is a MOSFET, it can be characterized by a channel length, L, and a width, W, where L is the spacing between the source and the drain, and W is the width of the pass transistor 14 in the direction perpendicular to the page of the drawing in FIG. 2. Assuming a constant applied voltage, a current passed by pass transistor 14 will scale proportionally to a ratio of W/L.
Successive TCCT based memory cells 10 are joined by three lines, a bit line 26, a first word line (WL1) 28, and a second word line (WL2) 30. The bit line 26 connects a drain 32 of pass transistor 14 to successive TCCT based memory cells 10. In a similar fashion, pass transistor 14 includes a gate 34 that forms a portion of the first word line 28. Likewise, the gate-like device 16 forms a portion of the second word line 30.
Memory arrays of the prior art typically include a large number of memory cells that are each configurable to be in either of two states, a logical “1” state or a logical “0” state. The memory cells are typically arranged in rows and columns and are connected to a grid of word lines and bit lines. In this way any specific memory cell can be written to by applying a signal to the appropriate word lines. Similarly, the state of a memory cell is typically manifested as a signal on one of the bit lines. In order to correctly interpret the state of the memory cell from the signal on the bit line, memory arrays of the prior art typically rely on some form of a reference signal against which the signal on the bit line is compared.
One type of memory array of the prior art uses SRAM cells for the memory cells. A conventional SRAM cell stores a voltage and includes two access ports, data and data-bar, where data-bar is a complementary signal to data and serves as a reference. A sensing circuit for the conventional SRAM cell compares the voltages of data and data-bar to determine whether the SRAM cell is storing a ‘1’ or a ‘0.’
Another type of memory array of the prior art uses DRAM cells for the memory cells. A conventional DRAM cell is a capacitor and stores a charge to represent a logical state. When a DRAM cell is read it produces a voltage on a bit line. A typical reference cell for a DRAM memory array is a modified DRAM cell designed to store about half as much charge as the conventional DRAM cell. Accordingly, in a DRAM memory array the voltage produced by the DRAM cell is compared to the voltage produced by the reference cell to determine whether the DRAM cell is storing a ‘1’ or a ‘0.’
In comparison to the conventional SRAM cell, a TCCT-based memory cell has only a single port, namely a bit line. In further comparison to both the SRAM and DRAM cells, the TCCT-based memory cell does not produce a voltage but instead produces a current. More specifically, TCCT-based memory cell has an “on” state wherein it generates a current that is received by the bit line. The TCCT-based memory cell also has an “off” state wherein it produces essentially no current.
A typical reference cell to be used in a memory array of TCCT-based memory cells should produce a reference current with an amount that is somewhere within the range defined by the currents generated by TCCT-based memory cell in the “on” and “off” states, and preferably about half the magnitude of the current generated by a TCCT-based memory cell in the “on” state. It is well known, however, that the amount of current produced by a TCCT-based memory cell 10 varies as a function of temperature, and also varies according to variations in manufacturing and operating conditions (i.e., voltages), among other things.
In a typical TCCT-based memory cell there is only one single bit line that is pre-charged to a ground state. In order to sense a bit line level, a sense amplifier needs a reference bit line level that is between ground and a bit line high level. For this reason, a long period of time (typically picoseconds) is needed to sense a large enough change in voltage between the bit line and the reference bit line. Also, the size of the architecture can get quite large when using reference cells because each bit line in a single or open bit line memory architecture can have from thirty-two to more than a thousand TCCT-based memory cells coupled thereto.
Therefore, what is desired is a memory cell and sensing scheme capable of generating a large enough voltage margin during the “on” state in a relatively shorter time frame. Also, it is desired to reduce the size of the memory cell architecture so that chip size can be reduced.